Mohammad Yavari

Associate Professor

Department of Electrical Engineering

Amirkabir University of Technology (Tehran Polytechnic)

        

 

Books

M. Yavari, Solutions of Electronics I & II Tests, Electrical Engineering, National Masters Entrance Exams, vol. 4, 4th Edition published in 2019 (in Persian).

M. Yavari, Solutions of Electronics I & II Tests, Electrical Engineering, National Masters Entrance Exams, vol. 3, 10th Edition published in 2014 (in Persian).

Journal Papers

1.    B. Shirmohammadi and M. Yavari, “A Linear Wideband CMOS Balun-LNA with Balanced Loads,” IEEE Trans. on Circuits and Systems-II: Express Briefs, Aug. 2021. (pdf)

2.   M. Mirzahosseini and M. Yavari, “A Digital Background Calibration Technique for Pipelined ADCs Using Initial Estimation of Errors and Histogram-Base Methods,” Journal of Iranian Association of Electrical and Electronics Engineers, 2021. (non-ISI) (pdf)

3.   M. Haghi Kashani, M. Asghari, M. Yavari, and S. Mirabbasi, “A +7.6 dBm IIP3 2.4-GHz Double-Balanced Mixer with 10.5 dB NF in 65-nm CMOS,” IEEE Trans. on Circuits and Systems-II: Express Briefs, Published online: Apr. 12, 2021. (pdf)

4.  F. Alizadeh Arand and M. Yavari, “A Three-Stage NMC Operational Amplifier with Enhanced Slew Rate for Switched-Capacitor Circuits,” Analog Integrated Circuits and Signal Processing, vol. 106, no. 3, pp. 697-706, Mar. 2021; Published online: Jan 07, 2021. (pdf)

5.  M. Moradian Boanloo and M. Yavari, “A Low-Power High-Gain Low-Dropout Regulator for Implantable Biomedical Applications,” Circuits, Systems & Signal Processing, vol. 40, no. 3, pp. 1041-1060, Mar. 2021; Published online: Aug. 24, 2020. (pdf)

6.  M. Momeni and M. Yavari, “Shifting the sampled input signal in successive approximation register analog-to-digital converters to reduce the digital-to-analog converter switching energy and area,” International Journal of Circuit Theory and Applications, vol. 48, no. 11, pp. 1873-1886, Nov. 2020; Published online: July 26, 2020. (pdf)

7.  M. Yaghoobi, M. Haghi Kashani, M. Yavari, and S. Mirabbasi, “A 56-to-66 GHz CMOS Low-Power Phased-Array Receiver Front-End with Hybrid Phase Shifting Scheme,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 67, no. 11, pp. 4002-4014, Nov. 2020; Published online: July 22, 2020. (pdf)

8.   H. Mafi, M. Yargholi, and M. Yavari, and S. Mirabbasi, “Digital Calibration of Elements Mismatch in Multirate Predictive SAR ADCs,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 66, no. 12, pp. 4571-4581, Dec. 2019; Published online: Aug. 21, 2019. (pdf)

9.   M. Yaghoobi and M. Yavari, and H. Ghafoorifard, “A 17-to-24 GHz Low-Power Variable-Gain Low-Noise Amplifier in 65-nm CMOS for Phased-Array Receivers,” Circuits, Systems & Signal Processing, vol. 38, no. 12, pp. 5448-5466, Dec. 2019; Published online: June 17, 2019. (pdf)

10  M. Yaghoobi, M. Yavari, M. Haghi Kashani, H. Ghafoorifard, and S. Mirabbasi, “A 55-to-64 GHz Low-Power Small-Area LNA in 65-nm CMOS with 3.8 dB Average NF and ~12.8 dB Power Gain,” IEEE Microwave and Wireless Components Letters, vol. 29, no. 2, pp. 128-130, Feb. 2019. (pdf)

11. P. Solati and M. Yavari, “A Wideband High Linearity and Low-Noise CMOS Active Mixer Using the Derivative Superposition and Noise Cancellation Techniques,” Circuits, Systems & Signal Processing, vol. 38, no. 7, pp. 2910-2930, July 2019; Published online: Jan. 07, 2019. (pdf)

12  S. Barati and M. Yavari, “An Adaptive Continuous-Time Incremental S∆ ADC for Neural Recording Implants,” International Journal of Circuit Theory and Applications, vol. 47, no. 2, pp. 187-203, Feb. 2019; Published online: 22nd Nov. 2018. (pdf)

13. S. Barati and M. Yavari, “An Automatic Action Potential Detector for Neural Recording Implants,” Circuits, Systems & Signal Processing, vol. 38, no. 5, pp. 1923-1941, May 2019; Published online: 22nd Oct. 2018. (pdf)

14.  H. Mafi, M. Yargholi, and M. Yavari, “Statistics-Based Digital Background Calibration of Residue Amplifier Nonlinearity in Pipelined ADCs,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 65, no. 12, pp. 4097-4109, Dec. 2018; Published online: 16th July 2018. (pdf)

15. M. Barati and M. Yavari, “A power conversion chain with an internally-set voltage reference and reusing the power receiver coil for wireless bio-implants,” Microelectronics Journal, vol. 74, no. 4, pp. 69-78, Apr. 2018, Published online: 5th Feb. 2018. (pdf)

16. M. Tamaddon and M. Yavari, “An oscillatory noise-shaped quantizer for time-based continuous-time sigma-delta modulators,” International Journal of Circuit Theory and Applications, vol. 46, no. 3, pp. 384-400, Mar. 2018, Published online: 27th Sept. 2017. (pdf)

17.  T. Yousefi, A. Dabbaghian, and M. Yavari, “An Energy-Efficient DAC Switching Method for SAR ADCs,” IEEE Trans. on Circuits and Systems-II: Express Briefs, vol. 65, no. 1, pp. 41-45, Jan. 2018, Published online: 2nd March 2017. (pdf)

18.  M. Barati and M. Yavari, “A Power Efficient Buck-Boost Converter by Reusing the Coil Inductor for Wireless Bio-Implants,” International Journal of Circuit Theory and Applications, vol. 45, no. 11, pp. 1673-1685, Nov. 2017, Published online: 6th Feb. 2017. (pdf)

19. H. Mafi, M. Yargholi, and M. Yavari, “Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 64, no. 6, pp. 1504-1514, Jun. 2017, Published online: 30th Jan. 2017. (pdf)

20.  P. Gholami and M. Yavari, “Digital Background Calibration with Histogram of Decision Points in Pipelined ADCs,” IEEE Trans. on Circuits and Systems-II: Express Briefs, vol. 65, no. 1, pp. 16-20, Jan. 2018, Published online:  27th Jan. 2017. (pdf)

21.  M. A. Montazerolghaem, T. Moosazadeh, and M. Yavari, “A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, pp. 1563-1567, Apr. 2017, Published online: 9th Jan. 2017. (pdf)

22.  M. Shahghasemi and M. Yavari, “MASH ΣΔ Modulators with a Noise-Shaped Two-Step ADC in the Second Stage,” Integration, the VLSI Journal, vol. 56, no. 1, pp. 77-85, Jan. 2017, Published online: Oct. 20, 2016. (pdf)

23  B. Khazaeili and M. Yavari, “A Simple Structure for MASH SD Modulators with Highly Reduced In-Band Quantization Noise,” Circuits, Systems & Signal Processing, vol. 36, no. 5, pp. 2125-2153, May 2017, Published online: Sept. 02, 2016. (pdf)

24.  M. Tamaddon and M. Yavari, “High-Performance Time-Based Continuous-Time Sigma-Delta Modulators Using Single-Opamp Resonator and Noise-Shaped Quantizer,” Microelectronics Journal, vol. 56, no. 10, pp. 110-121, Oct. 2016, Published online: 29th Aug. 2016. (pdf)

25.  M. Tamaddon and M. Yavari, “Time-Mode Signal Quantization for Use in Sigma-Delta Modulators,” Amirkabir International Journal of Science & Research (Electrical & Electronics Engineering), vol. 48, no. 1, pp. 53-61, June 2016. (pdf)

26  Z. Hojati and M. Yavari, “An NTF-Enhanced Incremental ΣΔ Modulator Using A SAR Quantizer,” Integration, the VLSI Journal, vol. 55, no. 9, pp. 212-219, Sept. 2016, Published online: 16th June 2016. (pdf)

27.  M. Asghari and M. Yavari, “An IIP3 Enhancement Technique for CMOS Active Mixers with a Source-Degenerated Transconductance Stage,” Microelectronics Journal, vol. 50, no. 4, pp. 44-49, Apr. 2016, Published online: 22nd Feb. 2016. (pdf)

28.  H. Mafi, M. Yavari, and H. Shamsi, “Digital Calibration of DAC Unit Elements Mismatch in Pipelined ADCs,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 63, no. 1, pp. 34-45, Jan. 2016. (pdf)

29.  H. Mafi, M. Yavari, and S. Sadigh Behzadi, “Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs,” Circuits, Systems & Signal Processing (Springer), vol. 35, no. 10, pp. 3675-3699, Oct. 2016; published online: Dec. 24, 2015. (pdf)

30. A. Bafandeh and M. Yavari, “Digital Calibration of Amplifier Finite DC Gain and Gain-Bandwidth in MASH ΣΔ Modulators,” IEEE Trans. on Circuits and Systems-II: Express Briefs, vol. 63, no. 4, pp. 321-325, Apr. 2016, Published online: Nov. 25, 2015. (pdf)

31. H. Pakniat and M. Yavari, “System level design and optimization of single-loop CT sigma-delta modulators for high resolution wideband applications,” Microelectronics Journal, vol. 46, pp. 1073-1081, published online: Sept. 14, 2015. (pdf)

32. M. Tamaddon and M. Yavari, “A Wideband Time-Based Continuous-Time Sigma-Delta Modulator with 2nd Order Noise-Coupling Based on Passive Elements,” International Journal of Circuit Theory and Applications, vol. 44, pp. 759-779, published online: June 16, 2015. (pdf)

33. T. Moosazadeh and M. Yavari, “A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods,” IEEE Trans. on Circuits and Systems-II, vol. 62, no. 9, pp. 826-830, Sept. 2015, published online: May 21, 2015. (pdf)

34. M. A. Montazerolghaem, T. Moosazadeh, and M. Yavari, “A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs,” IEEE Trans. on Circuits and Systems-II, vol. 62, no. 9, pp. 841-845, Sept. 2015, published online: May 21, 2015. (pdf)

35. R. Inanlou and M. Yavari, “A simple structure for noise-shaping SAR ADC in 90 nm CMOS technology,” International Journal of Electronics and Communications, vol. 69, no. 8, pp. 1085-1093, May 2015. (pdf)

36. M. Tamaddon and M. Yavari, “An NTF-Enhanced Time-Based Continuous-Time Sigma-Delta Modulator,” Analog Integrated Circuits and Signal Processing, vol. 85, no. 2, pp. 283-297, published online: May 24, 2015. (pdf)

37. S. Golabi and M. Yavari, “A  Three-Stage Class AB Operational Amplifier with Enhanced Slew Rate for Switched-Capacitor Circuits,” Analog Integrated Circuits and Signal Processing, vol. 83, no. 1, pp. 111-118, Apr. 2015, published online: Mar. 03, 2015. (pdf)

38. M. Asghari and M. Yavari, “Using the Gate-Bulk Interaction and a Fundamental Current Injection to Attenuate IM3 and IM2 Currents in RF Transconductors,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 1, pp. 223-232, Jan. 2016, Firstly published online: Feb. 20, 2015. (pdf)

39. B. Mazhabjafari and M. Yavari, “A UWB CMOS Low-Noise Amplifier with Noise Reduction and Linearity Improvement Techniques,” Microelectronics Journal, vol. 46, no. 2, pp. 198-206, Feb. 2015. (pdf)

40. M. Shahghasemi, R. Inanlou, and M. Yavari, “An Error-Feedback Noise-Shaping SAR ADC in 90 nm CMOS,” Analog Integrated Circuits and Signal Processing, Springer, vol. 81, no. 3, pp. 805-814, published online: Oct. 28, 2014. (pdf)

41. M. Asghari and M. Yavari, “Second-order intermodulation cancelation and conversion-gain enhancement techniques for CMOS active mixers,” International Journal of Circuit Theory and Applications, vol. 43, no. 10, pp. 1508-1522, Oct. 2015, published online: Sept. 29, 2014. (pdf)

42. N. Hajamini and M. Yavari, “An LO Architecture with Novel Wide Locking Range, Quadrature Output RILFDs and ILROs for Cognitive Radio Applications,” Analog Integrated Circuits and Signal Processing, vol. 80, no. 3, pp. 483-498, published online: July 04, 2014. (pdf)

43. S. Golabi and M. Yavari, “Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits,” Analog Integrated Circuits and Signal Processing, Springer, vol. 80, no. 2, pp. 195-208, Aug. 2014, published online: May 25, 2014. (pdf)

44. A. Shafti and M. Yavari, “A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS,” Analog Integrated Circuits and Signal Processing, Springer, vol. 80, no. 1, pp. 141-151, published online: Apr. 20, 2014. (pdf)

45. M. Yavari and T. Moosazadeh, “A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits,” Analog Integrated Circuits and Signal Processing, Springer, vol. 79, no. 3, pp. 589-598, Jun. 2014, published online: Apr. 02, 2014. (pdf)

46. E. Rahimi and M. Yavari, “Energy-efficient high-accuracy switching method for SAR ADCs,” IET Electronics Letters, vol. 50, no. 7, pp. 499-501, Mar. 27, 2014. (pdf)

47.  T. Moosazadeh and M. Yavari, “A pseudo-differential current-reuse structure for opamp-sharing pipelined analog-to-digital converters,” International Journal of Circuit Theory and Applications, vol. 43, no. 7, pp. 917-928, firstly published online: Feb. 27, 2014. (pdf)

48.  B. Khazaeili and M. Yavari, “MASH ΣΔ modulator with highly reduced in-band quantization noise,” IET Electronics Letters, vol. 50, no. 3, pp. 161-163, Jan. 30, 2014. (pdf)

49.  M. Asghari and M. Yavari, “Using interaction between two nonlinear systems to improve IIP3 in active mixers,” IET Electronics Letters, vol. 50, no. 2, pp. 76-77, Jan. 16, 2014. (pdf)

50. T. Moosazadeh and M. Yavari, “A high-performance pseudo-differential pipelined ADC with a novel class-AB gain boosting inverter,” Analog Integrated Circuits and Signal Processing, Springer, vol. 79, no. 2, pp. 255-266, published online: Dec. 25, 2013. (pdf)

51. R. Inanlou and M. Yavari, “A 10-Bit 0.5 V 100 kS/s SAR ADC with A New Rail-to-Rail Comparator for Energy Limited Applications,” Journal of Circuits, Systems, and Computers, vol. 23, no. 2, pp. 1450026-1-18, published online: Dec. 17, 2013. (pdf)

52.  H. Pakniat and M. Yavari, “A Time-Domain Noise-Coupling Technique for Continuous-Time Sigma-Delta Modulators,” Analog Integrated Circuits and Signal Processing, Springer, vol. 78, pp. 439-452, published online: Nov. 1, 2013. (pdf)

53. R. Inanlou, M. Shahghasemi, and M. Yavari, “A Noise-Shaping SAR ADC for Energy Limited Applications in 90 nm CMOS Technology,” Analog Integrated Circuits and Signal Processing, Springer, vol. 77, pp. 257-269, Oct. 2013. (pdf)

54. H. Pakniat and M. Yavari, “A Σ∆-FIR-DAC for Multi-Bit Σ∆ Modulators,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 60, no. 9, pp. 2321-2332, Sept. 2013. (pdf)

55. B. Zeinali, T. Moosazadeh, M. Yavari, and A. Rodriguez-Vazquez, “Equalization-Based Digital Background Calibration Technique for Pipelined ADCs,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 322-333, Feb. 2014, Firstly Published Online at 12th Feb. 2013. (pdf)

56. M. Khoshakhlagh and M. Yavari, “An Efficient Threshold Voltage Generation for SAR ADCs,” Analog Integrated Circuits and Signal Processing, Springer, vol. 75, no. 1, pp. 161-169, Apr. 2013. (pdf)

57. M. Mojarad and M. Yavari, “A Low Power Four-Stage Amplifier for Driving Large Capacitive Loads,” International Journal of Circuit Theory and Applications, vol. 42, no. 9, pp. 978-988, Sept. 2014, Firstly published online at 24th Jan. 2013. (pdf)

58.  F. Ataei and M. Yavari, “A Very Low Noise Wideband Class-C CMOS LC VCO,” Journal of Circuits, Systems, and Computers, World Scientific Publishing Company, vol. 21, no. 4, pp. 1250033-1-1250033-10, June 2012. (pdf)

59.  B. H. Seyedhosseinzadeh and M. Yavari, “An Efficient Low-Power Sigma-Delta Modulator for Multi-Standard Wireless Applications,” Journal of Circuits, Systems, and Computers, World Scientific Publishing Company, vol. 21, no. 4, pp. 1250028-1-1250028-20, June 2012. (pdf)

60.  Z. Sohrabi and M. Yavari, “A 13 bit 10 MHz Bandwidth MASH 3-2 Σ∆ Modulator in 90 nm CMOS,” International Journal of Circuit Theory and Applications, vol. 41, no. 11, pp. 1136-1153, Nov. 2013, Firstly Published Online at 17th April 2012. (pdf)

61.  M. H. Maghami and M. Yavari, “A Hybrid CT/DT Double-Sampled SMASH Σ∆ Modulator for Broadband Applications in 90 nm CMOS Technology,” Analog Integrated Circuits and Signal Processing, Springer (Special Issue of ICECS 2009), vol. 73, no. 1, pp. 101-114, Oct. 2012, Firstly Published Online at 14th Jan. 2012. (pdf)

62. M. Barati and M. Yavari, “A Linearization Technique for Active Mixers in Zero-IF Receivers with Inherent Balun,” IEICE Electron. Express, vol. 8, no. 24, pp. 2080-2086, Dec. 2011. (pdf)

63.  M. Yavari, “A Design Procedure for CMOS Three-Stage NMC Amplifiers,” IEICE Trans. Fundamentals, vol. E94-A, no. 2, pp. 639-645, Feb. 2011. (pdf)

64. T. Moosazadeh and M. Yavari, “A Novel Digital Calibration Technique for Pipelined ADCs,” IEICE Electron. Express, vol. 7, no. 23, pp. 1741-1746, Dec. 2010. (pdf)

65. M. H. Maghami and M. Yavari, “Low-Voltage Double-Sampled Hybrid CT/DT Σ∆ Modulator for Wideband Applications,” Journal of Circuits, Systems, and Computers, World Scientific, vol. 19, no. 8, pp. 1743-1751, Dec. 2010. (pdf)

66. M. Yavari, “Active-Feedback Single Miller Capacitor Frequency Compensation Techniques for Three-Stage Amplifiers,” Journal of Circuits, Systems, and Computers, World Scientific, vol. 19, no. 7, pp. 1381-1398, Nov. 2010. (pdf)

67. M. S. Mehrjoo and M. Yavari, “A New Input Matching Technique for Ultra Wideband LNAs,” IEICE Electron. Express, vol. 7, no.18, pp. 1376-1381, 25th Sept. 2010. (pdf)

68.  M. Yavari, “Single-Stage Class AB Operational Amplifier for SC Circuits,” IET Electronics Letters, vol. 46, no.14, pp. 977-979, 8th July 2010. (pdf)

69. S. Abdinia and M. Yavari, “A Low-Voltage Low-Power 10-bit 200 MS/s Pipelined ADC in 90nm CMOS,” Journal of Circuits, Systems, and Computers, World Scientific Publishing Company, vol. 19, no. 2, pp. 393-405, April 2010. (pdf)

70.  M. Jalalifar and M. Yavari, “A New Frequency Compensation Technique in Three Stage Amplifiers with Active Feedback,” Majlesi Journal of Electrical Engineering, vol. 4, no. 1, pp. 7-12, Mar. 2010.  (pdf)

71. M. Yavari, “A New Class AB Folded-Cascode Operational Amplifier,” IEICE Electron. Express, vol. 6, no. 7, pp. 395-402, Apr. 2009. (pdf)

72. A. Mirvakili, M. Yavari, and F. Raissi, “A Linear Current-Reused LNA for 3.1-10.6 GHz UWB Receivers,” IEICE Electron. Express, vol. 5, no. 21, pp. 908-914, Nov. 2008. (pdf) 

73. M. Yavari, O. Shoaei, and A. Rodriguez-Vazquez, “Double-Sampling Single-Loop SD Modulator Topologies for Broadband Applications,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 53, no. 4, pp. 314-318, Apr. 2006. (pdf)

74. M. Yavari, “Hybrid Cascode Compensation for Two-Stage CMOS Opamps,” IEICE Transactions on Electronics, Special Section on Analog Circuit and Device Technologies, vol. E88-C, no. 6, pp. 1161-1165, Jun. 2005. (pdf)

75. M. Yavari and O. Shoaei, “Efficient Double-Sampled Cascaded SD Modulator Topologies for Low OSRs,” IEICE Electron. Express, vol. 2, no. 13, pp. 404-410, Jul. 2005. (pdf)

76.  M. Yavari, N. Maghari, and O. Shoaei, “An Accurate Analysis of Slew-Rate for Two-Stage CMOS Opamps,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 52, no. 3, pp. 164-167, Mar. 2005. (pdf)

77.  M. Yavari and O. Shoaei, “Low-Voltage Low-Power Fast-Settling CMOS Operational Transconductance Amplifiers for Switched-Capacitor Applications,” IEE Proceedings on Circuits, Devices, and Systems, vol. 151, no. 6, pp. 573-578, Dec. 2004. (pdf)

78.   M. Yavari and O. Shoaei, “A Novel Fully-Differential Class AB Folded-Cascode OTA,” IEICE Electron. Express, vol. 1, no. 13, pp. 358-362, Oct. 2004. (pdf)

79.   M. Yavari and O. Shoaei, “Design of Very Low-Voltage High-Speed Sigma-Delta Modulators,” Journal of Faculty of Engineering (in Persian), University of Tehran, Iran, no. 3, vol. 38, pp. 441-459, Aug. 2004. (pdf)

80.  M. Yavari, O. Shoaei, and F. Svelto, “Low-Voltage Sigma-Delta Modulator Topologies for Broadband Communications Applications,” IEICE Transactions on Electronics, Special Section on Analog Circuit and Device Technologies, Vol. E87-C, no. 6, pp. 964-975, Jun. 2004. (pdf)

81.   M. Yavari and O. Shoaei, “Design a 3.3-V 18-bit Sigma-Delta Modulator for Digital Audio Applications,” Journal of Faculty of Engineering (in Persian), University of Tehran, Iran, no. 3, pp. 333-344, Dec. 2002. (pdf)

 

Conference Papers

1.    A. Ahrar and M. Yavari, “A Digital Method for Offset Cancellation of Fully Dynamic Latched Comparators,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, May 2021.

2. A. Karimlou and M. Yavari, “A Time-Based Analogue-to-Digital Converter for ECG Applications,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, May 2021.

3.  A. Mahsafar and M. Yavari, “A High Dynamic Range Differential Rectifier for RF Energy Harvesting,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, May 2021.

4.  M. Yousefirad and M. Yavari, “Kick-back Noise Reduction and Offset Cancellation Technique for Dynamic Latch Comparator,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, May 2021.

5.   A. Ahrar and M. Yavari, “A 14-bit SAR ADC with Calibration for Comparator Offset and Capacitive DAC Mismatch,” 2nd Iranian Conference on Microelectronics, pp. 1-5, Dec. 2020.

6.   B. Shirmohammadi and M. Yavari, “A highly linear wideband balun-LNA with symmetrical loads,” 2nd Iranian Conference on Microelectronics, pp. 1-5, Dec. 2020. (pdf)

7.  F. Alizadeh Arand and M. Yavari, “A Comprehensive Analysis of the Noise Power of Three-Stage OTAs in Switched-Capacitor Circuits,” Iranian Conference on Electrical Engineering (ICEE), Tabriz, Iran, Aug. 2020. (pdf)

8.   F. Ansari and M. Yavari, “A High Input Impedance Fully-Differential Chopper Amplifier for Closed-­Loop Neural Recording,” Iranian Conference on Electrical Engineering (ICEE), Tabriz, Iran, Aug. 2020.

9. B. Shirmohammadi and M. Yavari, “A Low Power Wideband Balun-LNA Employing Local Feedback, Modified Current-Bleeding Technique and Balanced Loads,” Iranian Conference on Electrical Engineering (ICEE), Tabriz, Iran, Aug. 2020. (pdf)

10. P. Solati and M. Yavari, “A Wide-Band CMOS Active Mixer with Linearity Improvement Technique,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 271-275, May 2017. (pdf)

11.  M. Barati and M. Yavari, “A Power Efficient Buck-Boost Converter by Reusing the Coil Inductor for Wireless Bio-Implants,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 431-434, May 2017. (pdf)

12.  M. S. Sadr, H. Ghafoorifard, M. Yavari, and S. Sheikhaei, “A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application,” Iranian Conference on Electrical Engineering (ICEE), Shiraz, Iran, pp. 810-815, May 2016. (pdf)

13.  M. A. Montazerolghaem, T. Moosazadeh, and M. Yavari, “A Fully Digital Calibration Technique for Nonlinearity Correction in Pipelined ADCs,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 1296-1300, May 2015. (pdf)

14.  M. Tamaddon and M. Yavari, “Realization of the 2nd-order NTF Enhancement in a Time-Encoded Continuous-Time Sigma-Delta Modulator Using Passive Elements,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 1203-1208, May 2015. (pdf)

15.  M. Asghari and M. Yavari, “A High IIP2 and IIP3 CMOS Down-Conversion Active Mixer,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 351-354, May 2014. (pdf)

16.   S. Golabi and M. Yavari, “High-Speed Three-Stage Operational Transconductance Amplifiers for Switched-Capacitor Circuits,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 413-417, May 2014. (pdf)

17.  B. Khazaeili and M. Yavari, “A Simple Global Resonation Strategy for Wideband Discrete-Time MASH ΣΔ Modulators,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 334-337, May 2014 (Awarded as the Best Paper). (pdf)

18.  B. Mazhabjafari and M. Yavari, “A 2.6-13.7 GHz Highly Linear CMOS Low Noise Amplifier for UWB Applications,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 296-299, May 2014. (pdf)

19.  M. Tamaddon and M. Yavari, “Design of a Continuous-Time ΣΔ Modulator Using the Time Domain Quantization Approach,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 215-219, May 2014. (pdf)

20.  N. Hajamini and M. Yavari, “A Ring-Type ILFD with Locking Range of 91% for Divide-by-4 and 40% for Divide-by-8 with Quadrature Outputs,” Iranian Conference on Electrical Engineering (ICEE), Mashad, Iran, May 2013. (pdf)

21.  M. Barati, B. Mazhabjafari, and M. Yavari, “A New Linearization Technique for CMOS Low Noise Amplifiers with Balun Circuitry,” Iranian Conference on Electrical Engineering (ICEE), Mashad, Iran, May 2013. (pdf)

22.  N. Ebrahimi Seraji and M. Yavari, “On the Design and Optimization of a Switched-Capacitor Interface Circuit for MEMS Capacitive Sensors,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 286-290, May 2012. (pdf)

23.  M. Mojarad and M. Yavari, “A Fast Settling On-Chip Low-Dropout Regulator with a Robust Frequency Compensation Scheme,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 291-294, May 2012. (pdf)

24.  M. Khoshakhlagh and M. Yavari, “A SAR ADC with an Efficient Threshold Voltage Generation,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 301-304, May 2012. (pdf)

25.  M. S. Mehrjoo, A. Ansari and M. Yavari, “A Noise Reduction Technique for Wideband LNAs in Low-Power Digital TV Applications,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 305-308, May 2012. (pdf)

26.  A. Ansari and M. Yavari, “A Very Wideband Low Noise Amplifier for Cognitive Radios,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Beirut, pp. 623-626, Dec. 2011. (pdf)

27.  M. Mojarad and M. Yavari, “A Novel Frequency Compensation Scheme for On-Chip Low-Dropout Voltage Regulators,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Beirut, pp. 318-321, Dec. 2011. (pdf)

28.  H. Pakniat and M. Yavari, “Dual Quantization Continuous Time SD Modulators with Spectrally Shaped Feedback,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Beirut, pp. 414-417, Dec. 2011. (pdf)

29.  B. Zeinali and M. Yavari, “A New Digital Background Correction Algorithm with Non-Precision Calibration Signals for Pipelined ADCs,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Beirut, pp. 418-421, Dec. 2011. (pdf)

30.  F. Ataei and M. Yavari, “A 2.2 GHz High-Swing Class-C VCO with Wide Tuning Range,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, Aug. 2011. (pdf)

31.  N. Ebrahimi Seraji and M. Yavari, “Minimum Detectable Capacitance in Capacitive Readout Circuits,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, Aug. 2011. (pdf)

32.  T. Moosazadeh and M. Yavari, “A 10-Bit 100-MSample/s Pipelined Analog-to-Digital Converter Using Digital Calibration Technique,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 388-392, May 2011. (pdf)

33.  F. Ataei and M. Yavari, “A Wideband Dual-Mode VCO with Analog and Digital Automatic Amplitude Control Circuitry,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 54-59, May 2011. (pdf)

34.  M. R. Ashraf and M. Yavari, “A 10-bit 250MS/s Pipelined ADC with a Merged S/H & 1st Stage Using an Optimal Opamp Sharing Technique,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 325-329, May 2011. (pdf)

35.  M. S. Mehrjoo and M. Yavari, “A Low Power UWB Very Low Noise Amplifier Using an Improved Noise Reduction Technique,” IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, pp. 277-280, May 2011. (pdf)

36.  M. Barati and M. Yavari, “A Highly Linear Mixer with Inherent Balun Using A New Technique to Remove Common Mode Currents,” IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, pp. 1884-1887, May 2011. (pdf)

37.  T. Moosazadeh and M. Yavari, “A Fully Digital Calibration Technique for Nonlinearity Correction in Pipelined ADCs,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, pp. 126-129, Dec. 2010. (pdf)

38.  M. R. Ashraf and M. Yavari, “A High Speed 1.5-Bit Mismatch-Insensitive Multiplying Digital-to-Analog Converter,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, pp. 776-779, Dec. 2010. (pdf)

39.  B. H. Seyedhosseinzadeh and M. Yavari, “A Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, pp. 1135-1138, Dec. 2010. (pdf)

40.  M. S. Mehrjoo and M. Yavari, “A Low-Power Noise Reduction Technique for Broadband CMOS Low-Noise Amplifiers,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, pp. 174-177, Dec. 2010. (pdf)

41.  B. H. Seyedhosseinzadeh and M. Yavari, “A MATLAB Toolbox Synthesizing Reconfigurable Delta-Sigma Modulators for Multi-Standard Wireless Applications,” 5th European Conference on Circuits and Systems for Communications (ECCSC), Belgrade, Serbia, pp. 204-207, Nov. 2010. (pdf)

42.  M. H. Maghami and M. Yavari, “Hybrid CT/DT Resonation-Based Cascade Σ∆ Modulators for Broadband Low-Voltage Applications,” 5th European Conference on Circuits and Systems for Communications (ECCSC), Belgrade, Serbia, pp. 107-110, Nov. 2010. (pdf)

43.  T. Moosazadeh and M. Yavari, “A Novel Digital Background Calibration Technique for Pipelined ADCs,” 5th European Conference on Circuits and Systems for Communications (ECCSC), Belgrade, Serbia, pp. 127-130, Nov. 2010. (pdf)

44.  H. Pakniat, M. Yavari, and R. Lotfi, “A Digital Background Correction Technique Combined with DWA for DAC Mismatch Errors in Multibit SD ADCs,” IEEE International Symposium on Circuits and Systems (ISCAS), Paris, pp. 293-296, May 2010. (pdf)

45.  T. Moosazadeh and M. Yavari, “A Simple Digital Background Gain Error Calibration Technique for Pipelined ADCs,” Iranian Conference on Electrical Engineering (ICEE), Isfahan, Iran, pp. 437-441, May 2010. (pdf)

46.  H. Pakniat and M. Yavari, “A Digital Calibration Technique Combined with DWA for Multibit SD ADCs,” Iranian Conference on Electrical Engineering (ICEE), Isfahan, Iran, May 2010. (pdf)

47.  S. Abdinia and M. Yavari, “A New Architecture for Low-Power High Speed Pipelined ADCs Using Double-Sampling and Opamp-Sharing Techniques,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Hemmamet, Tunisia, pp. 395-398, Dec. 2009. (pdf)

48.  M. Maghami and M. Yavari, “A Double-Sampled Hybrid CT/DT SMASH SD Modulator for Wideband Applications,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Hemmamet, Tunisia, pp. 41-44, Dec. 2009. (pdf)

49.  Y. Koolivand, M. Yavari, O. Shoaei, and A. Fotowat-Ahmady, “Low Voltage Low Power Techniques in Design of Zero IF CMOS Receivers, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Hemmamet, Tunisia, pp. 13-16, Dec. 2009. (pdf)

50.  H. Shokri and M. Yavari, “A Systematic Design Procedure for CMOS Three-Stage NMC Amplifiers,” European Conference on Circuit Theory and Design, ECCTD, Antalya, Turkey, pp. 499-502, Aug. 2009. (pdf)

51.  M. Yavari, “MASH Sigma-Delta Modulators with Reduced Sensitivity to the Circuit Non-Idealities,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 3126-3129, May 2009. (pdf)

52.  M. Maghami and M. Yavari, “Multirate Double-Sampling Hybrid CT/DT Sigma-Delta Modulators for Wideband Applications,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 2253-2256, May 2009. (pdf)

53.  A. Mirvakili and M. Yavari, “A Noise-Canceling CMOS LNA Design for the Upper Band of UWB DS-CDMA Receivers,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 217-220, May 2009. (pdf)

54.  H. Shamsi and M. Yavari, “On the Design of a Less Jitter Sensitive NTF for NRZ Multi-Bit Continuous-Time DS Modulators,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 1553-1556, May 2009. (pdf)

55.  M. Moayedi and M. Yavari, “High-Order Cascaded Sigma-Delta Modulators for Low-Voltage Wideband Applications,” Iranian Conference on Electrical Engineering (ICEE), pp. 400-403, Tehran, Iran, May 2009. (pdf)

56.  H. Shokri and M. Yavari, “Design of CMOS Three-Stage Amplifiers with Nested Miller Compensation,” Iranian Conference on Electrical Engineering (ICEE), pp. 404-407, Tehran, Iran, May 2009. (pdf)

57.  A. Mirvakili and M. Yavari, “A Linear Wideband CMOS LNA for 3-5 GHz UWB Systems,” International SOC Design Conference (ISOCC), Korea, vol. II, pp. 150-153, Nov. 2008. (pdf)

58.  M. Jalalifar, M. Yavari, and F. Raissi, “A Novel Topology in Reversed Nested Miller Compensation Using Dual-Active Capacitance,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 2270-2273, May 2008. (pdf)

59.  M. Jalalifar, M. Yavari, and F. Raissi, “A Novel Topology in RNMC Amplifiers with Single Miller Compensation Capacitor,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 296-299, May 2008. (pdf)

60.  M. Jalalifar, M. Yavari, and F. Raissi, “A Novel Frequency Compensation Technique in Three Stage Amplifiers with Active Feedback,” Iranian Conference on Electrical Engineering, ICEE, pp. 367-372, Tehran, Iran, May 2008. (pdf)

61.  M. Yavari and A. Rodriguez-Vazquez, “Accurate and Simple Modeling of Amplifier DC Gain Nonlinearity in Switched-Capacitor Circuits,” European Conference on Circuit Theory and Design, ECCTD, Sevilla, Spain, pp. 144-147, Aug. 2007. (pdf)

62.  M. Yavari, O. Shoaei, and A. Rodriguez-Vazquez, “Double-Sampled Cascaded Sigma-Delta Modulator Topologies for Low Oversampling Ratios” IEEE International Symposium on Circuits and Systems, ISCAS, pp. 597-600, May 2006. (pdf)

63.  M. Yavari, O. Shoaei, and A. Rodriguez-Vazquez, “Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation,” Design Automation and Test in Europe, DATE, Munich, Germany, pp. 144-149, March 2006. (pdf)

64.  M. Yavari, O. Shoaei, and A. Rodriguez-Vazquez, “Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications,” Design Automation and Test in Europe, DATE, Munich, Germany, pp. 399-404, March 2006. (pdf)

65.  M. Yavari and O. Shoaei, “A Novel Fully-Differential Class AB Folded-Cascode OTA for Switched- Capacitor Applications,” IEEE International Conference on Electronics, Circuits and Systems, ICECS, 2005. (pdf)

66.  M. Yavari and O. Shoaei, “High-Order Single-Loop Double-Sampling Sigma-Delta Modulator Topologies for Broadband Applications,” IEEE International Symposium on Circuits and Systems, ISCAS, Kobe, Japan, pp. 5593-5596, May 2005. (pdf)

67.  M. Yavari, O. Shoaei, and F. Svelto “Hybrid Cascode Compensation for Two-Stage CMOS Operational Amplifiers,” IEEE International Symposium on Circuits and Systems, ISCAS, Kobe, Japan, pp. 1565-1568, May 2005. (pdf)

68.  M. Yavari and O. Shoaei, “Low-Voltage Sigma-Delta Modulator Topologies for Broadband Applications,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. I 465-468, May 2004. (pdf)

69.  N. Maghari, M. Yavari, and O. Shoaei, “A Novel Model for the Slewing Behavior of Two-Stage CMOS OTAs,” IEEE International Symposium on Circuits and Systems, ISCAS, pp. I 553-556, May 2004. (pdf)

70.  M. Yavari and O. Shoaei, “Low-Voltage Low-Power Fast-Settling CMOS Operational Transconductance Amplifiers for Switched-Capacitor Applications,” International Symposium on Low Power Electronics and Design, ISLPED, Seoul, Korea, pp. 345-348, August 2003. (pdf)

71.  M. Yavari, H. Zare-Hoseini, M. Farazian, and O. Shoaei, “A New Compensation Technique for Two-Stage CMOS Operational Transconductance Amplifiers,” IEEE International Conference on Electronics, Circuits and Systems, ICECS, Sharjah, UAE, pp. 539-542, Dec. 2003. (pdf)

72.  H. Zare-Hoseini, M. Yavari, and O. Shoaei, “A Very Low-Noise Low-Power Integrator for a High-Resolution Delta-Sigma Modulator,” IEEE International Conference on Electronics, Circuits and Systems, ICECS, Sharjah, UAE, pp. 802-805, Dec. 2003. (pdf)

73.  M. Farazian, O. Shoaei, and M. Yavari, “Topology Selection for Low-Voltage Low-Power Wireless Receivers,” IEEE International Conference on Electronics, Circuits and Systems, ICECS, Sharjah, UAE, pp. 20-23, Dec. 2003. (pdf)

74.  M. Yavari and O. Shoaei, and A. Afzali-Kusha, “A Very Low-Voltage Low-Power and High-Resolution Sigma-Delta Modulator for Digital Audio in 0.25-mm CMOS,” IEEE International Symposium on Circuits and Systems, ISCAS, vol. 2, pp. 1045-1048, Bangkok, Thailand, May 2003. (pdf)

75.  M. Yavari, “A 1.2-V, 1.6-mW, 107-dB Dynamic Range, and 99.5-dB SNDR Sigma-Delta Modulator for Digital Audio in 0.25-mm CMOS,” Iranian Conference on Electrical Engineering, ICEE, vol. 1, pp. 514-521, Shiraz, Iran, May 2003. (pdf)

76.  M. Yavari and O. Shoaei, “Very Low-Voltage, Low-Power and Fast-Settling OTA for Switched-Capacitor Applications,” IEEE International Conference on Microelectronics, ICM, Beirut, Lebanon, pp. 10-13, Dec. 2002. (pdf)

77.  H. Shamsi, O. Shoaei, M. Yavari, and M. Y. Azizi, “A 160-MHz Six-Order Wideband Bandpass Sigma-Delta Modulator,” IEEE Asia Pacific Conference on Circuits and Systems, APCCAS, pp. 101-107, Dec. 2002. (pdf)

78.  M. Yavari, M.R. Hasanzadeh, J. Talebzadeh, and O. Shoaei, “A 3.3V 18 bit Digital Audio Sigma-Delta Modulator in 0.6-mm CMOS,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 640-643, Phoenix, Arizona, USA, May 2002. (pdf)

79.  J. Talebzadeh, M.R. Hasanzadeh, M. Yavari, and O. Shoaei, “A 10-bit 150-MS/s, Parallel Pipeline A/D Converter in 0.6mm CMOS,” IEEE International Symposium on Circuits and Systems, vol.3, pp. 133-136, Phoenix, Arizona, USA, May 2002. (pdf)

80.  J. Talebzadeh, M. Yavari, M.R. Hasanzadeh, and O. Shoaei, “A High-Speed and High- Resolution Parallel Pipeline A/D Converter in 0.6mm CMOS,” IEEE International Conference on Fundamentals of Electronics, Communications and Computer Sciences, ICFS, Tokyo, Japan, 2002. (pdf)

81.  M. Yavari, J. Talebzadeh, and O. Shoaei, “A High-Resolution & Low-Voltage Sigma-Delta Modulator in 0.6mm CMOS for Digital Audio,” Iranian Conference on Electrical Engineering, ICEE, Tabriz, Iran, May 2002. (pdf)

82.  M.R. Hasanzadeh, J. Talebzadeh, M. Yavari, and O. Shoaei, “A New-Method to Increase the Speed of Nyquist-Rate Current-Steering CMOS Digital-to-Analog Converters,” Iranian Conference on Electrical Engineering, ICEE, Tabriz, Iran, May 2002. (pdf)

83.  M. Yavari and O. Shoaei, “A 3.3V High-Resolution Sigma-Delta Modulator for Digital Audio,” IEEE International Conference on Microelectronics, ICM, Rabat, Morocco, pp. 129-132, Oct. 2001. (pdf)

84.  M. Yavari and O. Shoaei, “A 3.3 V Second-Order Sigma-Delta Modulator for Digital Audio,” Iranian Conference on Electrical Engineering, ICEE, Tehran, Iran, May 2001. (pdf)

85.  M. Yavari, “The Design and Implementation of Adaptive Digital Filters using DLMS Algorithm,” in 4th Iranian Student Conference on Electrical Engineering (ISCEE), Sept. 2001. (pdf)

86.  M. Yavari and O. Shoaei, “The Design of Sigma-Delta Modulators for Digital Audio,” in 4th Iranian Student Conference on Electrical Engineering (ISCEE), Sept. 2001. (pdf)

 

     Last updated on July 17, 2021.

 

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